Modeling Combinational Circuits Using Linear Word-level Structures

In many applications of circuit design and synthesis, it is natural and in some instances essential to manipulate logic functions and model circuits using word-level representations and arithmetic operations in contrast to bit-level representations and logic operations. This paper reviews linear word-level structures and formulates their properties for combinational circuit modeling. The paper addresses the following problem: given a library of gates with their corresponding word-level representations such as linear arithmetic expressions or respective graph structures, find a word-level model of an arbitrary combinational circuit/netlist using that library of gates and minimizing memory allocation and time delay requirements. We present a comprehensive study on linearization assuming various circuit processing strategies. In particular, we develop a new approach to manipulate linear word-level representations by means of cascades. The practical applicability of linear structures and developed algorithms is strengthen by considering the problem of timing analysis. All this is supported by the experimental study on benchmark circuits.